1. Field of the Invention
The present invention relates to display devices which automatically adjust the phase of sampling of a video signal, and particularly to improvement for eliminating the effect of jitter appearing in the phase of sampling to realize sampling at a proper phase.
2. Description of the Background Art
FIG. 12 is a block diagram showing the structure of a conventional display device as a background of the invention. This device is disclosed in Japanese Patent Application Laid-Open No. 11-177847 (1999), which is constructed as a liquid crystal display device which automatically adjusts the phase of sampling of an input analog video signal.
The input video signal is converted into digital form in an A/D converter 71. A video signal processing circuit 72 applies gamma correction etc. to the video signal in digital form and also converts the video signal into a proper form for an input signal to a liquid crystal panel 73. A PLL circuit 76 includes a voltage-controlled oscillator (VCO) 77 and a frequency divider 78, which multiplies the horizontal sync signal HD, one of the sync signals inputted with the video signal, to generate a clock having the same period as the video period. The divisional ratio of the frequency divider 78 determines the ratio of multiplication of the generated clock.
A phase correcting circuit 79 corrects the phase of the clock generated by the PLL circuit 76 and supplies a sampling clock VCLK to the A/D converter 71. The A/D converter 71 samples the video signal for digitization in synchronization with the sampling clock VCLK. The video signal digitized by the A/D converter 71 in each period of the sampling clock VCLK (=video period) is alternately referred to as left data DL and right data DR.
An operating unit 80 calculates an absolute difference value xcex94D=abs (DLxe2x88x92DR) for every two periods of the sampling clock VCLK; the absolute difference value is the absolute value of a difference between the left data DL and the right data DR. It also calculates a maximum absolute difference value Dmax=Max(xcex94D) which is a maximum value of the absolute difference values xcex94D in one frame. The sign xe2x80x9cabs ( )xe2x80x9d represents the absolute value.
A CPU 81 has a comparator 82 for comparing the maximum absolute difference values Dmax and a control circuit 83 for controlling the phase correcting circuit 79 on the basis of the result of the comparison to maximize the maximum absolute difference value Dmax. The control circuit 83 also serves to set the ratio of multiplication of the PLL circuit 76 in accordance with the format of the input video signal (e.g. VGA format etc.)
A timing generating circuit 74 generates a horizontal reference signal and a vertical reference signal indicating the starting points of horizontal and vertical scans on the basis of the sampling clock VCLK, horizontal sync signal HD and vertical sync signal VD. A liquid crystal driving circuit 75 generates a driving signal for driving the liquid crystal panel 73. The liquid crystal panel 73 receives the driving signal from the liquid crystal driving circuit 75 and the video signal from the video signal processing circuit 72 and displays the picture represented by the video signal.
FIGS. 13A to 13D, 14A to 14D and 15A to 15D are explanation diagrams illustrating the operation of adjusting the phase of the sampling clock VCLK. In these explanation diagrams, it is assumed for the sake of simplicity that the video signal represents an image pattern which alternately varies for each pixel as white, black, white, black . . . It is also assumed that the phase correcting circuit 79 can vary the phase of the clock within a variable-phase range of 0 to 360xc2x0 corresponding to the video period and in 32 steps from setting 0 to setting 31. In these diagrams, xe2x80x9cADC samplingxe2x80x9d shows the timing of sampling by the A/D converter 71.
FIGS. 13A to 13D show the characteristic of the maximum absolute difference value Dmax exhibited when the input video signal has a waveform close to a sine wave, FIGS. 14A to 14D show that exhibited when the input video signal has a waveform intermediate between a sine wave and a rectangular wave, and FIGS. 15A to 15D show that exhibited when the input video signal has a waveform close to a rectangular wave. It is assumed that the sampling clock VCLK and the video signal are in the phase relation shown in the diagrams when the phase value or the phase correction value set in the phase correcting circuit 79 is zero (that is, when the amount of delay by correction is 0xc2x0). The general principle of the description below is applicable whatever the phase relation is.
When the input video signal is close to a sine wave (FIGS. 13A to 13D), the maximum absolute difference value Dmax varies in upwardly convex curves as the phase value varies, where the phase value at the maximum corresponds to the optimum value and the phase value at the minimum corresponds to the worst value. As the video signal approaches a rectangular wave (FIGS. 14A to 14D and 15A to 15D), the maximum absolute difference value Dmax holds a maximum or nearby value in a wider range of the phase value. Accordingly, the optimum phase value is preferably obtained by detecting the worst value, i.e. a phase value at which the maximum absolute difference value Dmax becomes minimum, and setting the opposite phase shifted by 180xc2x0 from the worst value as the optimum phase value.
The conventional display device shown in FIG. 12 operates as explained above to automatically optimize the phase of sampling of the input analog video signal.
However, due to the effect of general frequency characteristic of the circuit, the input video signal approaches a sine wave as the video frequency (the reciprocal of the video period) becomes higher and approaches a rectangular wave as it becomes lower. Further, clock jitter usually appears in the clock outputted from the PLL circuit 76, which becomes larger as the video frequency becomes lower. Accordingly, when the video frequency is low, it is difficult to find the optimum phase value in the conventional display device of FIG. 12.
FIGS. 16A to 16D are explanation diagrams showing this problem, which shows an example of the characteristic of the maximum absolute difference value Dmax with a clock including jitter of 10%. As shown in FIGS. 16A to 16D, due to the effect of the jitter, the valleys of the maximum absolute difference value Dmax disappear and the maximum absolute difference value Dmax maintains a constant value almost in the whole range of the phase value. Then the optimum phase value cannot be found. Such effect of jitter becomes more serious as the video frequency becomes lower.
The present invention has been made to solve the aforementioned problem of conventional devices, and an object of the invention is to obtain a display device which can eliminate the effect of jitter appearing in the phase of sampling of the video signal so as to realize sampling at a proper phase regardless of the video frequency.
According to a first aspect of the present invention, a display device comprises: a sampling portion for sampling a video signal at a rate of a half period which is xc2xd times a video period of the video signal; a selecting portion for outputting as a display signal every other sampled signal which is the video signal sampled at the rate of the half period; a phase adjusting portion for adjusting the phase of the sampling performed by the sampling portion within a given variable-phase range; an absolute difference value calculating portion for calculating an absolute difference value which is, when the sampled signals are numbered with respect to one of the sampled signals in order of sampling time, the absolute value of a difference between an odd-numbered sampled signal and the next even-numbered sampled signal; a maximum absolute difference value calculating portion for calculating a maximum absolute difference value which is a maximum value in a plurality of the absolute difference values; and a phase control portion for controlling the phase adjusting portion under the restriction of the variable-phase range so that the display signal comprises the sampled signals sampled at a phase which is the closest to a phase set at or near the center of a rising transition in which the maximum absolute difference value increases as the phase delays.
Preferably, according to a second aspect, in the display device, the phase control portion adopts as the phase set at or near the center of a rising transition a phase with which the maximum absolute difference value increases past a given threshold or a phase shifted by the half period from a phase with which the maximum absolute difference value decreases past the given threshold.
Preferably, according to a third aspect, in the display device, the phase adjusting portion adopts the half period as the variable-phase range.
Preferably, according to a fourth aspect, in the display device, the selecting portion comprises a data switching portion capable of freely making a selection between the odd-numbered sampled signal and the even-numbered sampled signal, and the phase control portion controls the data switching portion as well as the phase adjusting portion so that the display signal comprises the sampled signals sampled at a phase which is the closest to the phase set at or near the center of the rising transition made as the phase delays.
Preferably, according to a fifth aspect, in the display device, the phase adjusting portion adopts the video period as the variable-phase range.
Preferably, according to a sixth aspect, in the display device, when the video period is larger than a given value, the phase control portion adopts as the phase set at or near the center of the rising transition a value which is corrected to reduce or cancel a displacement of the phase at the center of the rising transition on the basis of a known relation between the displacement and the magnitude of jitter occurring in the phase of the sampling.
Preferably, according to a seventh aspect, in the display device, the phase adjusting portion comprises a PLL circuit for multiplying a sync signal inputted together with the video signal to generate a clock which completes one cycle in the half period and a phase correcting circuit for correcting a phase of the clock generated by the PLL circuit within the variable-phase range and outputting the clock as a sampling clock, and the sampling portion samples the video signal in synchronization with the sampling clock.
According to the device of the first aspect, the video signal is sampled in a half period and the sampled signals sampled at a phase which is the closest to a phase set in or near the center of a rising transition are outputted as a display signal. The operation of searching for the phase set in or near the center of a rising transition is not hindered even if jitter appears in the sampling phase, so that the sampling can be done at a proper phase without being affected by the jitter.
According to the device of the second aspect, the phase set at or close to the center of a rising transition is determined on the basis of a comparison between the maximum absolute difference value and a given threshold, so that the structure of the phase control portion can be simplified.
According to the device of the third aspect, the phase adjusting portion adjusts the phase within the half period, so that a proper phase can always be obtained as the phase of the display signal.
According to the device of the fourth aspect, the selecting portion comprises a data switching portion which can freely select odd-numbered or even-numbered sampled signals and the phase control portion controls the data switching portion as well as the phase adjusting portion. Accordingly, despite the fact that the variable-phase range is the half period, an optimum phase coinciding with the phase set at or near the center of the rising transition can always be obtained as the phase of the display signal.
According to the device of the fifth aspect, the phase adjusting portion adjusts the phase within the range of the video period, so that an optimum phase coinciding with the phase set at or near the center of a rising transition can always be obtained as the phase of the display signal.
According to the device of the sixth aspect, when the video period is larger than a given value, a value corrected to reduce or cancel a displacement of the center-of-transition phase caused by jitter is adopted as the phase set at or near the center of a rising transition, so that a more proper sampled signal can be obtained as the display signal when jitter has a relatively serious effect.
According to the device of the seventh aspect, the phase adjusting portion is simply constructed using a PLL circuit and a phase correcting circuit.